1. Field of the Invention
The present invention generally relates to a package structure of a chip and a substrate and more specifically to formation of a stabilizing structure on the thin chip substrate in order to fasten the chip securely thereon.
2. The Prior Arts
As shown in FIG. 1, a traditional package structure for the chip and the substrate includes a thin chip substrate 1, a chip 50, a filling material 60 and a plastic molding material 90 and the thin chip substrate 1 includes a first circuit metal layer 16, a second circuit metal layer 18 and a dielectric layer 30.
Specifically, the first circuit metal layer 16 is inlaid into the dielectric layer 30 to form a co-plane. The second circuit metal layer 18 is formed on the dielectric layer 30 to fill up the holes in the dielectric layer 30 so as to connect electrically with the first circuit metal layer 16. The thin chip substrate 1 further includes a plurality of bonding pads 24 with a height higher than the co-plane connected to the first circuit metal layer 16, and a solder resist layer 20 covering the other side of the dielectric layer 30 and part of the second circuit metal layer 18.
The chip 50 has pins 52 connected to the bonding pads 24. The filling material 60 is injected into the part under the chip 50, which is connected to the bonding pads 24 via pins 52. Finally, the chip 50 and the thin chip substrate 1 are enclosed by the plastic molding material 90.
However, one of the shortcomings of the package structure in the prior arts is that the thin chip substrate has a thickness ranging from 70 to 150 μm, and the thin chip substrate and the chip package are generally produced by various companies using different processes. Further, the thin chip substrate is relatively thin and is easily warped, distorted or deformed during the process of transportation, injecting the filling material or enclosing by the plastic molding material. Consequently, the circuit design is greatly limited due to the offset loss in term of compensation, and no finer line width can be created.
Additionally, this package structure has a thickness of about 1.2 mm to 2.0 mm, which is obviously not able to meet the modern requirements of the electronic device, such as thinner and lighter. The cost of the package structure is also high because the plastic molding material is expensive such that it is hard to compete in the market.
Therefore, it is needed to provide a new package structure for effectively packaging the chip and the thin chip substrate to help designing much finer and thinner circuit to overcome the above problems in the prior arts.